The present invention relates to the technique effective in application to the device structure technique in a power semiconductor device (or semiconductor integrated circuit device) such as an IE (Injection Enhancement) type trench gate IGBT (Insulated Gate Bipolar Transistor) having an active cell and an inactive cell coexisting in the direction orthogonal to a trench gate.
JP-A-11-345969 discloses the technique that active cell areas and dummy cell areas are alternately disposed even in the direction of the trench gate in the IE type trench gate IGBT.
JP-A-10-326897 or U.S. Pat. No. 6,180,966 corresponding thereto discloses the technique that the surface directions of trench side walls of main cells and current detection cells are made identical to thereby make the characteristics of both cells identical in the trench gate IGBT.
JP-A-2007-194660 discloses the technique that the ratio of widths of active cells and floating cells in a main area and a current detection area is adjusted to thereby make the saturation current characteristics in both areas identical in the IE type trench gate IGBT.